1. Field of the Invention
The present invention relates to a boosting circuit for a semiconductor memory device, and in particular to a charge pump circuit which can vary an oscillation period in proportion to charge consumption of a charge pump.
2. Description of the Background Art
FIG. 1 illustrates a conventional charge pump circuit having a single oscillation period. As shown therein, the conventional charge pump circuit having the single oscillation period includes: a voltage divider 100 dividing a boosting voltage Vboot to a predetermined level; a comparator 102 comparing a divided voltage Vdiv outputted from the voltage divider 100 with a reference voltage Vref, and outputting a control voltage Vcon; a ring oscillator 104 outputting a pulse signal OSC having a fixed oscillation period in accordance with the control voltage Vcon outputted from the comparator 102; and a charge pump 106 performing a pumping operation in accordance with the pulse signal OSC outputted from the oscillator 104, and outputting a boosting voltage Vboot.
The ring oscillator 104 includes a plurality of inverters composing a ring. An RC integral circuit is inserted between the inverters, respectively. In addition, a last inverter of the plurality of inverters is a clocked inverter controlled by the control voltage Vcon of the comparator 102.
The charge pump 106 includes a first pumping capacitor Cp1 connected between an input node (a) and a first node (b); an output transistor 11 connected between the first node (b) and an output node (e), and transmitting a voltage of the first pumping capacitor Cp1 to the output node (e); an inverter IN1 and a second pumping capacitor Cp2 which are sequentially connected between the input node (a) and a second node (c); a diode type n-channel MOSFET 12 connected between a power supply voltage Vdd and the first node (b), and precharging the first pumping capacitor Cp1; a third pumping capacitor Cp3 connected between the input node (a) and a third node (d); and a diode type n-channel MOSFET 14 connected between a common node of the third node (d) and the output transistor 11 and the power supply voltage. Here, the first pumping capacitor Cp1 has a considerably large size, as compared with the second and third pumping capacitors Cp2, Cp3 which have an identical size.
The operation of the thusly-constituted charge pump circuit having the single oscillation period will now be described with reference to the accompanying drawings.
When the power supply voltage Vdd is applied, and the reference voltage Vref is inputted, a high-level control signal Vcon is outputted from the comparator 102, thereby enabling the ring oscillator 104. The enabled ring oscillator 104 outputs the pulse signal OSC having a fixed oscillation frequency. FIG. 4A illustrates an example of the pulse signal OSC outputted in a standby mode and an active mode in the conventional charge pump circuit having the single oscillation period. Accordingly, the charge pump 106 performs the pumping operation pursuant to the level of the pulse signal OSC outputted from the ring oscillator 104, thereby outputting the boosting voltage Vboot having a predetermined level.
The pumping operation of the charge pump will now be explained in more detail.
In case the pulse signal PSC is at a high level, the second pumping capacitor Cp2 is charged up with a voltage Vdd-Vth2 dropped by a threshold voltage Vth2 of the diode type n-channel MOSFET 12. When the pulse signal PSC is at a low level, the third pumping capacitor Cp3 is charged up with a voltage Vdd-Vth3 dropped by a threshold voltage Vth3 of the diode type n-channel MOSFET 14. Here, the voltage of the second and third nodes (c), (d) is Vdd-Vth2 and Vdd-Vth3, respectively.
Therefore, when it is presumed that the pulse signal OSC outputted from the ring oscillator 104 is at a low level, the second pumping capacitor Cp2 charged up at the Vdd-Vth2 level in a previous cycle carries out the pumping operation in accordance with the pulse signal OSC inverted in the inverter IN1, and thus the voltage of the Vdd-Vth1 level dropped by a threshold voltage Vth1 of the n-channel MOSFET 13 is precharged in the first node (b).
Thereafter, when the pulse signal OSC is transited from low to high, the first and third pumping capacitors Cp1, Cp3 perform the charge pumping operation, and the second pumping capacitor Cp2 is re-charged up at the Vdd-Vth2 level by the diode type n-channel MOSFET 12. As a result, the output transistor 11 is turned on by the voltage of the third node (d), and thus the voltage of the first node (b) boosted in the first pumping capacitor Cp1 is outputted into the output node (e) via the output transistor 11.
Accordingly, the voltage divider 100 divides the boosting voltage Vboot outputted from the charge pump 106, and the comparator 102 compares the divided voltage Vdiv outputted from the voltage divider 100 with the reference voltage Vref, and judges whether to keep performing the pumping operation of the charge pump 106. That is, when the divided voltage Vdiv is smaller than the reference voltage Vref, the ring oscillator 104 is enabled, thereby keep performing the pumping operation of the charge pump 106. In case the divided voltage Vdiv is greater than the reference voltage Vref, the ring oscillator 104 is disabled, thereby stopping the pumping operation of the charge pump 106.
However, in the conventional charge pump circuit having the single oscillation period, referring to FIG. 5, an oscillation frequency of the ring oscillator 104 is fixed to have a value f1 in order to maximally maintain the pumping efficiency Emax of the charge pump 106 both in the active mode and the standby mode. Accordingly, the conventional charge pump circuit having the single oscillation period has a disadvantage in that power consumption is increased in the standby mode.
In addition, in the conventional charge pump circuit having the single oscillation period, the first pumping capacitance Cp1 of the charge pump 106 must be maintained to be considerably large in order to satisfy a maximal charge consumption demand (maximal pumping efficiency). Consequently, the conventional charge pump circuit having the single oscillation period has another disadvantage in that a size of the charge pump 106 is increased by the first pumping capacitor Cp1.
FIG. 2 illustrates a conventional charge pump circuit having a dual oscillation period. As shown therein, the charge pump circuit having the dual oscillation period further includes an oscillator delay unit 108, as compared with the conventional charge pump circuit having the single oscillation period. The oscillator delay unit 108 is constituted identically to the ring oscillator 104, and connected to or disconnected from the ring oscillator 104 by first and second switches SW1, SW2.
Accordingly, the first and second switches SW1, SW2 are operated pursuant to a mode discriminating signal MDS, and connect the oscillator delay unit 108 to the ring oscillator 104 in the active mode, and disconnect the oscillator delay unit 108 therefrom in the standby mode. As a result, the oscillation frequency of the pulse signal OSC outputted from the ring oscillator 104 is fixed to have a different value in the active mode and the standby mode. That is to say, the oscillation frequency of the ring oscillator 104 is fixed to be a value f1 (high frequency) for satisfying the maximal charge consumption demand in the active mode, and to be a value (low frequency) for satisfying low charge consumption in the standby mode. FIG. 4B illustrates an example of the pulse signal OSC outputted in the standby mode and the active mode in the conventional charge pump circuit having the dual oscillation period.
However, in the conventional charge pump circuit having the dual oscillation period, the capacitance of the first pumping capacitor Cp1 must satisfy the maximal charge consumption demand in the active mode, identically to the conventional charge pump circuit having the single oscillation period. Therefore, as compared with the charge pump circuit having the single oscillation period, the charge pump circuit having the dual oscillation period has an advantage in that power consumption can be reduced. However, a size of the charge pump circuit is still increased due to the first pumping capacitor Cp1.
Also, the charge pump circuit having the dual oscillation period may drop the boosting voltage level due to unexpected charge consumption (current leakage) in the standby mode. Consequently, in case the operation of the semiconductor memory device is changed from the standby mode to the active mode, there is a disadvantage in that the pumping voltage cannot be rapidly restored to the boosting voltage level.